Peufeu's Electronic Stuff Unfinished projects since 1912

The two candidates

(click for PDF).

I experimented a bit on the "Simple IV" theme (right circuit in the attached PDF).

This circuit has desirable characteristics :
- Bandwidth : 10 MHz
- Input impedance : resistive, (2-3 ohms) up to 100 MHz, then falling
- Ringing and nasties : None
- Transistors used in current mode only (Vbe doesn't matter)

But it also has undesirable characteristics :
- It is not particularly linear (being open loop)
- PSRR isn't the best

I can't do anything for PSRR but, since the circuit has a constant power draw, it shouldn't be a problem, I'll just add a separate regulator for all the I/Vs.

I tried to make it more linear, then. Since the main source of error is transistor base current, I wanted to reinject this in the circuit somehow. Of course, it introduces positive feedback, so it makes nice oscillators.

CFPs are rather useless since they are too slow. With a CFP at the input, the impedance rises at HF.

Also, the simple circuit needs a bias on the input transistor base. The input impedance depends on this. So, the simple circuit is rather abstract, because it has the transistor base into ground for simulations.

The result is the other, a bit more complicated circuit. It is a lot more linear and has the same other characteristics. See attached PDF.

I tried various transistors, I wanted to use high-current types like BC337 because BC547 starts its beta droop right at the bias point used in this circuit. But either my spice model for BC337 is wrong, or this transistor has gremlins inside, beause it always oscillated no matter the circuit...

Maybe I should try cascoding with JFETs, also, but I have no ideas which to use.

Hawksford

I read the Hawksford paper. While the authors clearly did something that needed to be done, and did it well, there are a few things which bother me in their circuit.

First is the input impedance :

Red and blue are the two circuits in the above PDF. Impedance is a few ohms but constant and resistive (phase not shown, but it's flat). Green is Hawksford. Impedance is a lot lower then rises at HF and becomes inductive ; then falls again as it becomes capacitive. With a settling time of around 200 ns for a PCM1704, and delta-sigma DACs running at 6.something MHz, we need good HF behaviour.
(I really have no clue about what the DAC would prefer, the datasheets say nothing, this is mostly gut feeling).

I also didn't steal from the Hawksford topology because I don't like current mirrors in the signal path.
However Bricolo (Alex) told me he would implement a hawksford style IV ; we will try to make some comparisons.

How do the circuits work ?

You'll recognize the biasing current sources. These must be properly balanced to null output DC offset, so a DC servo will be needed.
Transistors whose Vbe is important (ie. the current sources) all operate at constant Vce and Ic. This is an important fact of BJT design, as Vbe depends nonlinearly on about all the operating parameters, including instantaneous temperature.

Q3 cascodes Q6 and keeps it safe from the output voltage variations.
Q1 and Q2 steer the DAC output current into the output resistor.

The sources of error (distortion and nonlinearities) are :
A- Q1-3 base currents
B- Q4-6 Vce variations which still get through the cascodes and influence the current sources.

From the simulations it results that the main error cause is A. Linear variation of base currents does not matter ; it just changes the output gain a little. What matters are nonlinear variations of base currents depending on :
- hFe variation (beta changes)
- nonlinear Cbc (only for the two output cascodes which don't operate at constant Vce).

These are caused by variation of operating parameters (Vce, Ic, instantaneous temperature).
Q1 is biased at around 15 mA for higher transconductance (lower input impedance). Q2-3 are biased at around 10 mA for headroom. DAC output current is +/- 1.2 mA.

Biasing Q1

Let's try the traditional biasing scheme.

There is something slow somewhere : the input impedance mighty sucks.

So, we should design a circuit which maintains the input impedance constant and low until it drops due to transistor parasitic capacitance, while reinjecting the base current in circuit to compensate for Q1 base current nonlinearities. Ergo :

Input impedance is a bit higher but nice and flat (pink curve). The two values show C1 of 960p (minimum value for flatness) and 470uF (lower impedance).

At low frequencies, Q146 holds the base of Q1 at the correct voltage. R10b provides some voltage offset and a time lag combined with C1. R11b is for biasing. C1 provides a short path to ground at HF so the input impedance stays flat.

Q146 reinjects Q1b's base current into the circuit, cancelling the nonlinearities. Without C1/R10b, this creates positive feedback and makes the circuit oscillate. The nice thing is that the error current is stored in C1 and then reinjected slowly into the circuit.

Q2:Q3 base currents

We use the same principle to reinject Q2/Q3 base currents into the circuit. The current source around Q7c can be replaced by a resistor around Q3c's base-emitter junction.

The key is that the error (base) current is stored in a capacitor and later slowly reinjected in the circuit.

Input impedance is the green curve on the above plot. Here is the frequency response for the 3 circuits (7a,8b,8c). Nice and flat.

Distortion simulations

Harmonics are in dB relative to the fundamental. Simulated at 2 kHz.
"sustained beta Transistors" means BC547/537 was replaced with a mix of 2SA970/2SC2240 and BCP53-16 / BCP56-16 where applicable.

Conclusions :
The simple (8b) I/V needs good transistors. The evolved version (8c) needs high beta transistors and compensates the nonlinearities. Distortion figures are excellent for an open-loop circuit.
Using 470uF for C1 prevents the error compensation on Q1 from working and distortion in circuit 8c becomes a bit worse, but input impedance is lower. The DAC will have its say on that.

Thanks to the forum members for helping on transistor selection !