I tracked my problem down to a long cable from
the JTAG device to the FPGA.
Apparently the Xilinx inputs are either VERY corrupted by
noise on the chip's ground or have some sort of negative
impedance characteristic -- they oscillate by themselves
when the input changes state.
A "SLOW" change in state on the "clock" line and the "problem" appears.
Either results in the same sort of problem.
Thus all the series resistors on FPGA traces.... In MOST
of the FPGA designs you look at !!!!!
jtag troubles - fixes
I tracked my problem down to a long cable from
the JTAG device to the FPGA.
Apparently the Xilinx inputs are either VERY corrupted by
noise on the chip's ground or have some sort of negative
impedance characteristic -- they oscillate by themselves
when the input changes state.
A "SLOW" change in state on the "clock" line and the "problem" appears.
Either results in the same sort of problem.
Thus all the series resistors on FPGA traces.... In MOST
of the FPGA designs you look at !!!!!